The present invention relates to the field of flash memories. More specifically, the present invention provides for an improved method and apparatus for programming and erasing flash memory cells.
A programmable read-only memory (PROM) is a type of nonvolatile memory. In other words, once data has been written into a PROM, it will remain there indefinitely, even when power to the PROM is removed. Typically, a PROM is arranged in an array of rows and columns of individual memory cells.
Although PROMs are nonvolatile, there are certain types that can be erased and reprogrammed. One of these is the electrically erasable programmable read-only memory (EEPROM or E2PROM). A “flash” EEPROM is a special type of EEPROM of which a large number of cells, e.g. a block, sector or page, can be electrically erased and reprogrammed as compared to being electrically erased and reprogrammed one byte at a time, which is done in non-flash EEPROMs.
Like other PROMs, a flash EEPROM retains data written into individual cells, even in the absence of power. The ability to retain data in memory in the absence of power and the ability to rewrite data in memory is provided by a floating gate within each cell. A conventional flash memory cell is constructed as a single field-effect transistor (FET) with a floating gate interposed between a control gate and a channel region of the transistor. By altering the charge stored in the floating gate, the state of the cell can be changed back and forth between a logic “high” state and a logic “low” state, thereby s allowing one bit of information to be stored therein. The two states are referred to as a “programmed” state and an “erased” state.
To program a cell, charge is added to the floating gate. Because the floating gate is insulated from the control gate, source, and drain of the cell, any charge placed on the floating gate remains there until removed by an erase process. Although the floating gate is completely insulated, charge can be added and removed using techniques described below and other known prior art techniques.
FIG. 1 shows a cell 10 with a control gate 12, a floating gate 14, a source 16 and a drain 18. Control gate 12 and floating gate 14 are separated from source 16 and drain 18, and from a substrate 11 into which the source 16 and drain 18 are formed, by an oxide 22 which may be formed by one or more layers of a suitable oxide material. Suitable openings in the oxide 22 are provided to allow for external connection to source 16 and drain 18. As shown, connections are provided to set Vg (control gate voltage), Vd (drain voltage), Vs (source voltage) and Vb (substrate voltage).
FIG. 2 shows how a flash EEPROM cell is typically arranged in an array 20 of rows and columns of individual memory cells 200. By applying appropriate voltages to a given word line and given bit line, a specific cell is selected for programming or erasing. Note that under all conditions the sources of each cell are grounded as a common source 202.
To more particularly illustrate the programming of a specific cell, consider the upper left cell in FIG. 2, which is associated with the intersection of Word Line 1 and Bit Line 1. (It is assumed that all cells are in an initial erased condition and have a logic level of “1”, i.e., an erased state.) To program the upper left cell, a positive voltage of, for example, approximately 8.5 volts, is applied to Word Line 1 and a positive voltage of, for example, approximately 4.5 volts, is applied to Bit Line 1. The non-selected Word and Bit Lines are either left floating or are biased to ground potential. The 4.5 volt difference between the cell's drain and source causes electrons to accelerate through the channel of the cell. With sufficient energy and with the aid of the 8.5 volts applied to the cell's gate, electrons tunnel into the floating gate of the transistor, thereby programming the cell to a logic level of “0”. To leave the upper left cell in an erased state, the cell is not biased into a channel hot electron bias condition. This programming state can be satisfied, for example, by ensuring that Bit Line 1 is grounded and Word Line 1 is biased to a negative voltage.